A semiconductor memory device such as a DRAM and an SRAM is mounted on many electronic devices which are popular at present. For example, the DRAM is provided with a plurality of memory cells. A capacitance element and a switching transistor are provided for each of the plurality of memory cells. One of source/drain electrodes of the switching transistor is connected with one of electrodes of the capacitance element. The other of the source/drain electrodes of the switching transistor is connected with a data line and an intermediate voltage between a power supply voltage and the ground voltage is supplied. Also, the intermediate voltage between the power supply voltage and the ground voltage is supplied to the other electrode of the capacitance element.
Most of the semiconductor memory devices available at present are compatible to a test mode. In the test mode, a test voltage is supplied to the one end (hereinafter, the cell counter electrode voltage) of the capacitance element of the DRAM cell and the operation is tested. At that time, a defective memory cell is detected, and it is replaced with a substitution memory cell if possible. The semiconductor memory device corresponding to the test mode is known (For example, refer to Patent Literature 1).
The Patent Literature 1 describes a technique of a semiconductor memory device which uses ½ of a power supply voltage (hereinafter, ½Vcc) for setting a cell counter electrode voltage and precharging a digit line. Referring to the Patent Literature 1, a conventional semiconductor memory device is provided with a HVCC level generating circuit 101 which generates a ½Vcc level and a short-circuiting circuit 103 to short-circuit the cell counter electrode line HVCP1 and the precharge line HVCD. The HVCC level generating circuit 101 is provided with the HVCC level generating section which generates the ½Vcc and a test circuit which has an on/off controlled transistor in response to a test mode signal.
Also, the short-circuiting circuit 103 is provided with a test circuit which has an on/off controlled transistor in response to the test mode signal. One of the transistors is a transfer gate, and short-circuits the cell counter electrode line HVCP1 and the precharge line HVCD. At the time of the test mode, the transfer gate is set to an off-state in response to the test mode signal. Also, at this time, a test is carried out by setting the cell counter electrode line HVCP1 to the power supply voltage (Vcc) or the ground voltage (GND) in response to the test mode signal.
In the technique of the Patent Literature 1, a plurality of the short-circuiting circuits 103 are arranged in the cell array. A plurality of transfer gates sometimes causes increase of a chip area in the semiconductor memory device. A technique is known which is provided with a power supply circuit which generates a cell counter electrode voltage in the test mode separately from a power supply circuit which supplies a precharge voltage, in order to restrain the increase of the chip area (For example, Patent Literature 2).
Citation List:
[Patent Literature 1]: JP 2000-215660A
[Patent Literature 2]: JP-A-Heisei 06-44779